1. Field of the Invention
The present invention relates to a multiport memory comprising a storage section having dynamic memory cells and a serial port in the column direction of the storage section and, more particularly, a multiport memory used for an improvement of a data transfer function for transferring data of the memory cells to the serial port.
2. Description of the Related Art
The multiport memory is a memory which has one serial access memory port for inputting/outputting data in the column direction, independently of an input/output of one random access memory port (to be referred to as a RAM port hereinafter) consisting of dynamic memory cells. Such multiport memories have already been commercially available.
FIG. 3 is a block diagram showing an arrangement of a multiport memory. The RAM port includes memory cell array 10 serving as a storage section, row address buffer 11, row address decoder 12, column address buffer 13, column address decoder and selector 14, and input/output data buffer 15. On the other hand, an SAM (serial access memory) port includes serial data register 30, serial address counter 40, serial decoder and selector 50, and serial input/output data buffer 60. The arrangement in FIG. 3 also includes data transfer gate 20 for performing bidirectional data transfer between the RAM port and the SAM port and timing generator 70 for generating timing signals from external input clock signals RAS, CAS, WE, OE, SC, and SE. In consideration of an application of the multiport memory as a video memory, a dynamic memory cell having one transistor and one capacitor and a sense amplifier are suitable for memory cell array 10 in view of its integration density. For the sake of simplicity of the design, data transfer gate 20 consists of one MOSFET, and serial data register 30 consists of a flip flop circuit which is the same as in the memory cell of a static memory.
FIG. 4 shows a one-column arrangement of the above multiport memory. In FIG. 4, reference symbol A denotes a RAM port section; and B, an SAM port section. Reference symbol T1 denotes a switching transistor of the memory cell of the dynamic memory; CS, a storage capacitor thereof; WL, a word line; BL and BL, a pair of bit lines; N1, a data storage node; .phi.DT, a data transfer gate signal; and DR and DR, storage nodes of the data register in the SAM port. Reference numeral 1 denotes a bit line sense amplifier of the RAM port; 2, MOSFETs constituting a data transfer gate; and 3, flip-flop circuits constituting a data register in the SAM port using the static memory cells.
FIG. 5 is a timing chart showing an operation according to the prior art in a data transfer cycle for supplying the memory cell data of RAM port A, i.e., the potential of node N1, to data register 3 in SAM port B. Although a precharge potential of the pair of bit lines BL and BL will be described by exemplifying the potential at 1/2 VDD level, this applies to other cases. A case wherein cell data stores "1", i.e., node N1 is set at supply voltage level VDD is considered.
An operation of timing generator 70 in FIG. 3 is started at a trailing edge of external input clock RAS (row address strobe signal), and row address buffer 11 and decoder 12 are enabled, so that word line WL is selected and raised. Therefore, data of node N1 is read out on bit line BL. Sense amplifier 1 shown in FIG. 4 is enabled, and hence bit lines BL and BL are connected to VDD and ground VSS, respectively, thereby determining the potential of node N1. Then, transfer of data of RAM port A which is read out on this bit line BL to SAM port B is started at a leading edge of external input clock OE (output enable signal). In other words, a pulse of internal signal .phi.DT (data transfer gate signal) is generated in response to the leading edge of clock OE, and storage nodes DR and DR of the data register are connected to bit lines BL and BL, respectively. As a result, data register 3 is updated so that lines DR and BL, and DR and BL are set at identical potentials.
On the other hand, when time tRAS has elapsed after signal RAS is disabled, signal RAS is raised again, and Internal signal RSET (word line reset signal) is raised in synchronism with the leading edge of signal RAS. Word line WL is reset and bit lines BL and BL are equalized (set at equal potentials), thus setting a standby state for the next cycle for the RAM port.
In such a data transfer method according to the prior art, internal signal RSET in the RAM port and data transfer gate signal .phi.DT are asynchronous to cause the following disadvantages.
More specifically, as shown in FIG. 5, signal OE is raised after signal RAS is raised, and data transfer gate pulse .phi.DT is generated. When data of RAM port A to be transferred is set at an inverted level of the data stored in data register 30, since power supply voltages VDD and VSS are instantaneously connected with each other, the potential of bit line BL is decreased by .DELTA.V. Therefore, when signal RSET is raised and word line WL is reset, a decreased "1" voltage appears at data storage node N1 of the memory cell, and a sufficient margin for holding data in a dynamic memory may not be assured. In addition, when the leading edge of signal OE is further delayed, word line WL is reset and the potential of bit line BL is set to be equal to that of bit line BL. Therefore, the RAM port data to be transferred to the SAM port may be erased and an erroneous operation in the data transfer cycle may occur.
In order to solve the above problems by the prior art, the leading edge of signal OE in the data transfer cycle must be defined to be advanced from the leading edge of signal RAS in actual operation. Therefore, the margin of the timings of external input signal RAS and OE must be decreased, thereby interfering with an application technique of the multiport (dual port) memory.